Strategies towards high performance (high-resolution/linearity) time-to-digital converters on field-programmable gate arrays

Time-correlated single-photon counting (TCSPC) technology has become popular in scientific research and industrial applications, such as high-energy physics, bio-sensing, non-invasion health monitoring, and 3D imaging. Because of the increasing demand for high-precision time measurements, time-to-digital converters (TDCs) have attracted attention since the 1970s. As a fully digital solution, TDCs are portable and have great potential for multichannel applications compared to bulky and expensive time-to-amplitude converters (TACs). A TDC can be implemented in ASIC and FPGA devices. Due to the low cost, flexibility, and short development cycle, FPGA-TDCs have become promising. Starting with a literature review, three original FPGA-TDCs with outstanding performance are introduced. The first design is the first efficient wave union (WU) based TDC implemented in Xilinx UltraScale (20 nm) FPGAs with a bubble-free sub-TDL structure. Combining with other existing methods, the resolution is further enhanced to 1.23 ps. The second TDC has been designed for LiDAR applications, especially in driver-less vehicles. Using the proposed new calibration method, the resolution is adjustable (50, 80, and 100 ps), and the linearity is exceptionally high (INL pk-pk and INL pk-pk are lower than 0.05 LSB). Meanwhile, a software tool has been open-sourced with a graphic user interface (GUI) to predict TDCs’ performance. In the third TDC, an onboard automatic calibration (AC) function has been realized by exploiting Xilinx ZYNQ SoC architectures. The test results show the robustness of the proposed method. Without the manual calibration, the AC function enables FPGA-TDCs to be applied in commercial products where mass production is required.Time-correlated single-photon counting (TCSPC) technology has become popular in scientific research and industrial applications, such as high-energy physics, bio-sensing, non-invasion health monitoring, and 3D imaging. Because of the increasing demand for high-precision time measurements, time-to-digital converters (TDCs) have attracted attention since the 1970s. As a fully digital solution, TDCs are portable and have great potential for multichannel applications compared to bulky and expensive time-to-amplitude converters (TACs). A TDC can be implemented in ASIC and FPGA devices. Due to the low cost, flexibility, and short development cycle, FPGA-TDCs have become promising. Starting with a literature review, three original FPGA-TDCs with outstanding performance are introduced. The first design is the first efficient wave union (WU) based TDC implemented in Xilinx UltraScale (20 nm) FPGAs with a bubble-free sub-TDL structure. Combining with other existing methods, the resolution is further enhanced to 1.23 ps. The second TDC has been designed for LiDAR applications, especially in driver-less vehicles. Using the proposed new calibration method, the resolution is adjustable (50, 80, and 100 ps), and the linearity is exceptionally high (INL pk-pk and INL pk-pk are lower than 0.05 LSB). Meanwhile, a software tool has been open-sourced with a graphic user interface (GUI) to predict TDCs’ performance. In the third TDC, an onboard automatic calibration (AC) function has been realized by exploiting Xilinx ZYNQ SoC architectures. The test results show the robustness of the proposed method. Without the manual calibration, the AC function enables FPGA-TDCs to be applied in commercial products where mass production is required

Efficient time-to-digital converters in 20 nm FPGAs with wave union methods

The wave union (WU) method is a well-known method in time-to-digital converters (TDCs) and can improve TDC performances without consuming extra logic resources. However, a famous earlier study concluded that the WU method is not suitable for UltraScale field-programmable gate array (FPGA) devices, due to more severe bubble errors. This paper proves otherwise and presents new strategies to pursue high-resolution TDCs in Xilinx UltraScale 20 nm FPGAs. Combining our new sub-tapped delay line (sub-TDL) architecture (effective in removing bubbles and zero-width bins) and the WU method, we found that the wave union method is still powerful in UltraScale devices. We also compared the proposed TDC with the TDC combining the dual sampling (DS) structure and the sub-TDL technique. A binning method is introduced to improve the linearity. Moreover, we derived a formula of the total measurement uncertainties for a single-stage TDL-TDC to obtain its root-mean-square (RMS) resolution. Compared with previously published FPGA-TDCs, we presented (for the first time) much more detailed precision analysis for single-TDL TDCs

Multi-channel high-linearity time-to-digital converters in 20 nm and 28 nm FPGAs for LiDAR applications

This paper proposes a new calibration method, the mixed-binning method, to pursue a TDC with high linearity in field-programmable gate arrays (FPGAs). This method can reduce the nonlinearity caused by large clock skews in FPGAs efficiently. Therefore, a wide dynamic range tapped delay line (TDL) TDC has been developed with maintained linearity. We evaluated this method in Xilinx 20nm UltraScale FPGAs and Xilinx 28nm Virtex-7 FPGAs. Results conduct that this method is perfectly suitable for driverless vehicle applications which require high linearity with an acceptable resolution. The proposed method also has great potentials for multi-channel applications, due to the low logic resource consumption. For a quick proof-of-concept demonstration, an 8-channel solution has also been implemented. It can be further extended to a 64-channel version soon

Multichannel time-to-digital converters with automatic calibration in Xilinx Zynq-7000 FPGA devices

This paper proposes a weighted histogram method and an automatic calibration architecture to implement high-linearity time-to-digital converters (TDCs) 16 in low-cost advanced RISC machine (ARM)-based field-programmable gate arrays (FPGAs). The proposed method significantly reduces nonlinearity induced by nonuniform bins. It offers automatic calibration without manual interventions using ARM processors. Besides, our design is cost-effective in hardware consumption. We implemented and evaluated a 32-channel TDC system in a low-cost Zynq-7000 ARM-based FPGA, in which the programable logic is equivalent to a 28 nm Artix-7 FPGA. The proposed TDC offers a resolution of 9.83 ps (LSB = 9.83 ps) with good uniformity, achieving an averaged peak-peak differential nonlinearity (DNLpk-pk) of 0.27 LSB, and an averaged peak-to-peak integral nonlinearity 28 (INLpk-pk) of 0.67LSB

128-channel high-linearity resolution- adjustable time-to-digital converters for LiDAR applications : software predictions and hardware implementations

This paper proposes a new calibration method, called the mixed-binning (MB) method, to pursue high-linearity time-to-digital converters (TDCs) for light detection and ranging (LiDAR) applications. The proposed TDCs were developed using tapped delay-line (TDL) cells in field-programmable gate arrays (FPGAs). With the MB method, we implemented a resolution-adjustable TDC showing excellent linearity in Xilinx UltraScale FPGAs. We demonstrate a 128-channel TDC to show that the proposed method is cost-effective in logic resources. We also developed a software tool to predict the performances of TDL-based TDCs robustly. Results from both software analysis and hardware implementations are in a good agreement and show that the proposed design has great potential for multichannel applications; the averaged DNL_(pk-pk) and INL_(pk-pk) are close to or even less than 0.05 LSB in multichannel designs

Low hardware consumption, resolution-configurable gray code oscillator time-to- digital converters implemented in 16nm, 20nm and 28nm FPGAs

This paper presents a low-hardware consumption, resolution-configurable, automatically calibrating gray code oscillator time-to-digital converter (GCO-TDC) in Xilinx 16nm UltraScale+, 20nm UltraScale and 28nm Virtex-7 field-programmable gate arrays (FPGAs). The proposed TDC utilizes LUTs as delay elements and has several innovations: 1) a sampling matrix structure to improve the resolution. 2) a virtual bin calibration method (VBCM) to achieve configurable resolutions and automatic calibration. 3) hardware implementation of the VBCM in standard FPGA devices. We implemented and evaluated a 16-channel TDC system in all three FPGAs. The UltraScale+ version achieved the best resolution (least significant bit, LSB) of 20.97 ps with 0.09 LSB averaged peak-to-peak differential nonlinearity (DNLpk-pk). The UltraScale and Virtex-7 versions achieved the best resolutions of 36.01 ps with 0.10 LSB averaged DNLpk-pk and 34.84 ps with 0.08 LSB averaged DNLpk-pk, respectively

Spatial resolution improved fluorescence lifetime imaging via deep learning

We present a deep learning approach to obtain high-resolution (HR) fluorescence lifetime images from low-resolution (LR) images acquired from Fluorescence Lifetime IMaging (FLIM) systems. We first proposed a theoretical method for training neural networks to generate massive semi-synthetic FLIM data with various cellular morphologies, a sizeable dynamic lifetime range, and complex decay components. We then developed a degrading model to obtain LR-HR pairs and created a hybrid neural network, the Spatial Resolution Improved FLIM net (SRI-FLIMnet), to simultaneously estimate fluorescence lifetimes and realize the nonlinear transformation from LR to HR images. The evaluative results demonstrate SRI-FLIMnet’s superior performance in reconstructing spatial information from limited pixel resolution. We also verified SRI-FLIMnet using experimental images of bacterial infected mouse raw macrophage cells. Results show that the proposed data generation method and SRIFLIMnet efficiently achieve superior spatial resolution for FLIM applications. Our study provides a solution for fast obtaining HR FLIM images

Functional connectivity of the human amygdala in health and in depression

To analyze the functioning of the amygdala in depression, we performed the first voxel-level resting state functional-connectivity neuroimaging analysis of depression of voxels in the amygdala with all other voxels in the brain, with 336 patients with major depressive disorder and 350 controls. Amygdala voxels had decreased functional connectivity with the orbitofrontal cortex, temporal lobe areas, including the temporal pole, inferior temporal gyrus, and the parahippocampal gyrus. The reductions in the strengths of the functional connectivity of the amygdala voxels with the medial orbitofrontal cortex and temporal lobe voxels were correlated with increases in the Beck Depression Inventory score and in the duration of illness measures of depression. Parcellation analysis in 350 healthy controls based on voxel-level functional connectivity showed that the basal division of the amygdala has high functional connectivity with medial orbitofrontal cortex areas, and the dorsolateral amygdala has strong functional connectivity with the lateral orbitofrontal cortex and related ventral parts of the inferior frontal gyrus. In depression, the basal amygdala division had especially reduced functional connectivity with the medial orbitofrontal cortex which is involved in reward; and the dorsolateral amygdala subdivision had relatively reduced functional connectivity with the lateral orbitofrontal cortex which is involved in non-reward

Functional connectivity of the anterior cingulate cortex in depression and in health

The first voxel-level resting-state functional connectivity (FC) neuroimaging analysis of depression of the anterior cingulate cortex (ACC) showed in 282 patients with major depressive disorder compared with 254 controls, some higher, and some lower FCs. However, in 125 unmedicated patients, primarily increases of FC were found: of the subcallosal anterior cingulate with the lateral orbitofrontal cortex, of the pregenual/supracallosal anterior cingulate with the medial orbitofrontal cortex, and of parts of the anterior cingulate with the inferior frontal gyrus, superior parietal lobule, and with early cortical visual areas. In the 157 medicated patients, these and other FCs were lower than in the unmedicated group. Parcellation was performed based on the FC of individual ACC voxels in healthy controls. A pregenual subdivision had high FC with medial orbitofrontal cortex areas, and a supracallosal subdivision had high FC with lateral orbitofrontal cortex and inferior frontal gyrus. The high FC in depression between the lateral orbitofrontal cortex and the subcallosal parts of the ACC provides a mechanism for more non-reward information transmission to the ACC, contributing to depression. The high FC between the medial orbitofrontal cortex and supracallosal ACC in depression may also contribute to depressive symptoms

Dynamic fluorescence lifetime sensing with CMOS single-photon avalanche diode arrays and deep learning processors

Measuring fluorescence lifetimes of fast-moving cells or particles have broad applications in biomedical sciences. This paper presents a dynamic fluorescence lifetime sensing (DFLS) system based on the time-correlated single-photon counting (TCSPC) principle. It integrates a CMOS 192 × 128 single-photon avalanche diode (SPAD) array, offering an enormous photon-counting throughput without pile-up effects. We also proposed a quantized convolutional neural network (QCNN) algorithm and designed a field-programmable gate array embedded processor for fluorescence lifetime determinations. The processor uses a simple architecture, showing unparallel advantages in accuracy, analysis speed, and power consumption. It can resolve fluorescence lifetimes against disturbing noise. We evaluated the DFLS system using fluorescence dyes and fluorophore-tagged microspheres. The system can effectively measure fluorescence lifetimes within a single exposure period of the SPAD sensor, paving the way for portable time-resolved devices and shows potential in various applications